The present invention relates to the non-contact measurement of leakage current of p-n junctions in test structures located in the scribe lanes of IC product wafers using a junction photo-voltage (JPV) technique
As the number of transistors per IC increases, the contribution to dynamic and standby power drains from transistor junction leakage currents poses increasing limitations to the implementation of advanced technology designs and a serious power drain for battery-powered systems. Many process factors associated with the fabrication of ultra-shallow junctions (USJ), with junction depths less than 30 nm, contribute to the increasing junction leakage current density as transistor size is scaled to smaller dimensions. Monitoring junction leakage current on in-process IC product wafers provides timely input for tuning manufacturing conditions to minimize leakage current levels.
The present invention provides a method and apparatus for non-contact measurements of p-n junction leakage current with spatial resolution (<100 um) consistent with the dimension of test structures in IC wafer scribe lanes.